1. Technical Field
The present application relates to an apparatus, method and program for controlling a networked communications bus for use in a semiconductor chip.
2. Description of the Related Art
Recently, in the fields of built-in computers and general-purpose processors which use an SoC (System on Chip), there is a growing demand for semiconductor chips with enhanced performance. And as the performance of a semiconductor chip has been enhanced these days to meet such a demand, the requested bandwidth of data to be transferred through communications buses on the chip has increased so much that the bandwidth of the communications buses needs to be increased, too. In order to broaden the bandwidth of a communications bus at a low bus operating frequency, a lot of people have paid much attention these days to a Network-on-chip (NoC) which shares a bus line between multiple processors and which can contribute to using given resources more efficiently.
Japanese Patent No. 4485574 discloses a method for increasing the promptness of response to memory access requests in a general SoC configuration in which a plurality of initiators and memory controllers are connected together via an NoC and in which there are both rate-ensured initiators which need to ensure an access at a constant rate during a predetermined period and non-rate-ensured initiators which submit access requests to a memory at irregular, non-easily-predictable intervals.
FIG. 1 illustrates a configuration for the SoC disclosed in Japanese Patent No. 4485574. On detecting an access request submitted by a rate-ensured initiator 201, an access management section 203 in a memory controller 206 checks out the number of times of accesses to determine whether or not this is an access at a predetermined rate or less, and keeps the decision result on record and manages the record. Only when there is no access request submitted by any other initiator 202, an access arbitrator 205 approves the access request at the predetermined rate or more that has been submitted by the rate-ensured initiator 201. If the access arbitrator 205 detects an access request submitted by the non-rate-ensured initiator 202 before providing arbitration for the access request from the rate-ensured initiator 201, then the access arbitrator 205 provides arbitration for the access request from the non-rate-ensured initiator 202 earlier than the access request from the rate-ensured initiator 201. The order of arbitration is reversed because the rate-ensured initiator 201 has already made accesses at the predetermined rate or more. By performing such processing, the promptness of response to the access request from the non-rate-ensured initiator 202 can be increased.